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ISCAS
2003
IEEE
89views Hardware» more  ISCAS 2003»
15 years 3 months ago
Synthesizing checkers for on-line verification of System-on-Chip designs
In modern System-on-Chip (SoC) designs verification becomes the major bottleneck. Since by using state-of-theart techniques complete designs cannot be fully formally verified, it ...
Rolf Drechsler
MICRO
2008
IEEE
137views Hardware» more  MICRO 2008»
14 years 9 months ago
Verification of chip multiprocessor memory systems using a relaxed scoreboard
Verification of chip multiprocessor memory systems remains challenging. While formal methods have been used to validate protocols, simulation is still the dominant method used to ...
Ofer Shacham, Megan Wachs, Alex Solomatnikov, Amin...
CHARME
2001
Springer
92views Hardware» more  CHARME 2001»
15 years 1 months ago
Induction-Oriented Formal Verification in Symmetric Interconnection Networks
The framework of this paper is the formal specification and proof of applications distributed on symmetric interconnection networks, e.g. the torus or the hypercube. The algorithms...
Eric Gascard, Laurence Pierre
HCI
2009
14 years 7 months ago
High-Fidelity Prototyping of Interactive Systems Can Be Formal Too
The design of safety critical systems calls for advanced software engineering models, methods and tools in order to meet the safety requirements that will avoid putting human life ...
Philippe A. Palanque, Jean-François Ladry, ...
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HICSS
2007
IEEE
125views Biometrics» more  HICSS 2007»
15 years 4 months ago
Stochastic Formal Methods: An Application to Accuracy of Numeric Software
— This paper provides a bound on the number of numeric operations (fixed or floating point) that can safely be performed before accuracy is lost. This work has important implic...
Marc Daumas, David Lester