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ISICT
2003
14 years 11 months ago
On the automated implementation of modal logics used to verify security protocols
: Formal verification provides a rigid and thorough means of evaluating the correctness of cryptographic protocols so that even subtle defects can be identified. As the application...
Tom Coffey, Reiner Dojen, Tomas Flanagan
DAC
2008
ACM
15 years 10 months ago
Construction of concrete verification models from C++
C++ based verification methodologies are now emerging as the preferred method for SOC design. However most of the verification involving the C++ models are simulation based. The c...
Malay Haldar, Gagandeep Singh, Saurabh Prabhakar, ...
ICSE
2001
IEEE-ACM
15 years 2 months ago
A Scalable Formal Method for Design and Automatic Checking of User Interfaces
The paper addresses the formal specification, design and implementation of the behavioral component of graphical user interfaces. The complex sequences of visual events and action...
Jean Berstel, Stefano Crespi-Reghizzi, Gilles Rous...
FDL
2008
IEEE
14 years 11 months ago
RTL Generation of Channel Architecture Templates for a Template-based SoC Design Flow
In this paper, we propose the design methodology for communication channel templates from formal specification to RTL description. In this flow, design and verification start from...
Jinhyun Cho, Soonwoo Choi, Soo Chae
VLSID
2001
IEEE
129views VLSI» more  VLSID 2001»
15 years 10 months ago
Design Of Provably Correct Storage Arrays
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann