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CONCUR
2006
Springer
15 years 1 months ago
Sanity Checks in Formal Verification
One of the advantages of temporal-logic model-checking tools is their ability to accompany a negative answer to the correctness query by a counterexample to the satisfaction of the...
Orna Kupferman
ATVA
2007
Springer
134views Hardware» more  ATVA 2007»
15 years 1 months ago
Formal Modeling and Verification of High-Availability Protocol for Network Security Appliances
One of the prerequisites for information society is secure and reliable communication among computing systems. Accordingly, network security appliances become key components of inf...
Moonzoo Kim
FMCAD
2006
Springer
15 years 1 months ago
Post-reboot Equivalence and Compositional Verification of Hardware
We introduce a finer concept of a Hardware Machine, where the set of post-reboot operation states is explicitly a part of the FSM definition. We formalize an ad-hoc flow of combin...
Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Z...
AINA
2003
IEEE
15 years 1 months ago
Formal Verification of Condition Data Flow Diagrams for Assurance of Correct Network Protocols
Condition Data Flow Diagrams (CDFDs) are a formalized notation resulting from the integration of Yourdon Data Flow Diagrams, Petri Nets, and pre-post notation. They are used in th...
Shaoying Liu
DAC
2009
ACM
15 years 10 months ago
Computing bounds for fault tolerance using formal techniques
Continuously shrinking feature sizes result in an increasing susceptibility of circuits to transient faults, e.g. due to environmental radiation. Approaches to implement fault tol...
André Sülflow, Görschwin Fey, Rol...