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FMCAD
2008
Springer
14 years 11 months ago
BackSpace: Formal Analysis for Post-Silicon Debug
Post-silicon debug is the problem of determining what's wrong when the fabricated chip of a new design behaves incorrectly. This problem now consumes over half of the overall ...
Flavio M. de Paula, Marcel Gort, Alan J. Hu, Steve...
ACSC
2004
IEEE
15 years 1 months ago
Automatic Derivation of Loop Termination Conditions to Support Verification
This paper introduces a repeatable and constructive approach to the analysis of loop progress and termination conditions in imperative programs. It is applicable to all loops for ...
Daniel Powell
FMCAD
2007
Springer
15 years 1 months ago
Boosting Verification by Automatic Tuning of Decision Procedures
Parameterized heuristics abound in computer aided design and verification, and manual tuning of the respective parameters is difficult and time-consuming. Very recent results from ...
Frank Hutter, Domagoj Babic, Holger H. Hoos, Alan ...
IWPSE
2010
IEEE
14 years 7 months ago
An exercise in iterative domain-specific language design
We describe our experiences with the process of designing a domain-specific language (DSL) and corresponding model transformations. The simultaneous development of the language an...
Marcel van Amstel, Mark van den Brand, Luc Engelen
FAC
2000
114views more  FAC 2000»
14 years 9 months ago
Representational Reasoning and Verification
Formal approaches to the design of interactive systems rely on reasoning about properties of the t a very high level of abstraction. Specifications to support such an approach typi...
Gavin J. Doherty, José Creissac Campos, Mic...