Sciweavers

3256 search results - page 76 / 652
» Applications of Formal Methods to System Design and Verifica...
Sort
View
DATE
2005
IEEE
164views Hardware» more  DATE 2005»
15 years 3 months ago
Automated Synthesis of Assertion Monitors using Visual Specifications
Automated synthesis of monitors from high-level properties plays a significant role in assertion-based verification. We present here a methodology to synthesize assertion monitors...
Ambar A. Gadkari, S. Ramesh
ENTCS
2008
139views more  ENTCS 2008»
14 years 10 months ago
Pervasive Compiler Verification - From Verified Programs to Verified Systems
We report in this paper on the formal verification of a simple compiler for the C-like programming language C0. The compiler correctness proof meets the special requirements of pe...
Dirk Leinenbach, Elena Petrova
ICSE
2004
IEEE-ACM
15 years 10 months ago
Assume-Guarantee Verification of Source Code with Design-Level Assumptions
Model checking is an automated technique that can be used to determine whether a system satisfies certain required properties. To address the "state explosion" problem a...
Dimitra Giannakopoulou, Corina S. Pasareanu, Jamie...
COMPSEC
2010
142views more  COMPSEC 2010»
14 years 6 months ago
Provably correct Java implementations of Spi Calculus security protocols specifications
Spi Calculus is an untyped high level modeling language for security protocols, used for formal protocols specification and verification. In this paper, a type system for the Spi ...
Alfredo Pironti, Riccardo Sisto
ICSE
2005
IEEE-ACM
15 years 10 months ago
Verification and change-impact analysis of access-control policies
Sensitive data are increasingly available on-line through the Web and other distributed protocols. This heightens the need to carefully control access to data. Control means not o...
Kathi Fisler, Shriram Krishnamurthi, Leo A. Meyero...