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ISPAN
2002
IEEE
15 years 11 months ago
Automatic Processor Lower Bound Formulas for Array Computations
In the directed acyclic graph (dag) model of algorithms, consider the following problem for precedence-constrained multiprocessor schedules for array computations: Given a sequenc...
Peter R. Cappello, Ömer Egecioglu
GLVLSI
2007
IEEE
166views VLSI» more  GLVLSI 2007»
15 years 10 months ago
Efficient pipelining for modular multiplication architectures in prime fields
This paper presents a pipelined architecture of a modular Montgomery multiplier, which is suitable to be used in public key coprocessors. Starting from a baseline implementation o...
Nele Mentens, Kazuo Sakiyama, Bart Preneel, Ingrid...
HM
2007
Springer
155views Optimization» more  HM 2007»
15 years 10 months ago
A Hybrid ILS Heuristic to the Referee Assignment Problem with an Embedded MIP Strategy
Optimization in sports is a field of increasing interest. A novel problem in sports management is the Referee Assignment Problem, in which a limited number of referees with differe...
Alexandre R. Duarte, Celso C. Ribeiro, Sebasti&aac...
EUROPAR
2008
Springer
15 years 8 months ago
Optimized Pipelined Parallel Merge Sort on the Cell BE
Chip multiprocessors designed for streaming applications such as Cell BE offer impressive peak performance but suffer from limited bandwidth to offchip main memory. As the number o...
Jörg Keller, Christoph W. Kessler
ATMOS
2010
172views Optimization» more  ATMOS 2010»
15 years 5 months ago
Column Generation Heuristic for a Rich Arc Routing Problem
In this paper we address a real world optimisation problem, the Rail Track Inspection Scheduling Problem (RTISP). This problem consists of scheduling network inspection tasks. The...
Sébastien Lannez, Christian Artigues, Jean ...