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ISLPED
1995
ACM
95views Hardware» more  ISLPED 1995»
15 years 9 months ago
Reducing the frequency of tag compares for low power I-cache design
In current processors, the cache controller, which contains the cache directory and other logic such as tag comparators, is active for each instruction fetch and is responsible fo...
Ramesh Panwar, David A. Rennels
169
Voted
LCPC
1995
Springer
15 years 9 months ago
Compiler Architectures for Heterogeneous Systems
Heterogeneous parallel systems incorporate diverse models of parallelism within a single machine or across machines and are better suited for diverse applications 25, 43, 30]. Thes...
Kathryn S. McKinley, Sharad Singhai, Glen E. Weave...
137
Voted
DBPL
1991
Springer
66views Database» more  DBPL 1991»
15 years 9 months ago
Rationale and Design of BULK
BULK is a very-high-level persistent programming language and environment for prototyping and implementing database applications. BULK provides sets and sequences as primitive typ...
Steve Rozen, Dennis Shasha
151
Voted
AOSD
2009
ACM
15 years 9 months ago
A generic and reflective debugging architecture to support runtime visibility and traceability of aspects
In this paper we present a generic, mirror-based debugging architecture that supports runtime visibility and traceability of aspect oriented (AO) software systems. Runtime visibil...
Wouter De Borger, Bert Lagaisse, Wouter Joosen
CISIS
2010
IEEE
15 years 9 months ago
Automatic Offloading of C++ for the Cell BE Processor: A Case Study Using Offload
Offload C++ is an extended version of the C++ language, together with a compiler and runtime system, for automatically offloading general-purpose C++ code to run on the Synergistic...
Alastair F. Donaldson, Uwe Dolinsky, Andrew Richar...
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