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DAC
2008
ACM
16 years 5 months ago
Scan chain clustering for test power reduction
An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-...
Christian G. Zoellin, Hans-Joachim Wunderlich, Jen...
DAC
2007
ACM
16 years 5 months ago
Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip
Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single gl...
Ümit Y. Ogras, Diana Marculescu, Puru Choudha...
DAC
1999
ACM
16 years 5 months ago
Behavioral Synthesis Techniques for Intellectual Property Protection
? The economic viability of the reusable core-based design paradigm depends on the development of techniques for intellectual property protection. We introduce the first dynamic wa...
Inki Hong, Miodrag Potkonjak
DAC
2004
ACM
16 years 5 months ago
Retargetable profiling for rapid, early system-level design space exploration
Fast and accurate estimation is critical for exploration of any dece in general. As we move to higher levels of abstraction, on of complete system designs at each level of abstrac...
Lukai Cai, Andreas Gerstlauer, Daniel Gajski
DAC
2004
ACM
16 years 5 months ago
Profile-guided microarchitectural floorplanning for deep submicron processor design
As process technology migrates to deep submicron with feature size less than 100nm, global wire delay is becoming a major hindrance in keeping the latency of intra-chip communicat...
Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watew...
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