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ICCD
2008
IEEE
117views Hardware» more  ICCD 2008»
16 years 1 months ago
RMA: A Read Miss-Based Spin-Down Algorithm using an NV cache
—It is an important issue to reduce the power consumption of a hard disk that takes a large amount of computer system’s power. As a new trend, an NV cache is used to make a dis...
Hyotaek Shim, Jaegeuk Kim, Dawoon Jung, Jin-Soo Ki...
ICCD
2007
IEEE
205views Hardware» more  ICCD 2007»
16 years 1 months ago
Hardware libraries: An architecture for economic acceleration in soft multi-core environments
In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to ...
David Meisner, Sherief Reda
136
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ICCD
2004
IEEE
107views Hardware» more  ICCD 2004»
16 years 1 months ago
Network-on-Chip: The Intelligence is in The Wire
In this paper we describe how Network-on-Chip (NoC) will be the next major challenge to implementing complex and function-rich applications in advanced manufacturing processes at ...
Gérard Mas, Philippe Martin
ICCAD
2006
IEEE
134views Hardware» more  ICCAD 2006»
16 years 1 months ago
A delay fault model for at-speed fault simulation and test generation
We describe a transition fault model, which is easy to simulate under test sequences that are applied at-speed, and provides a target for the generation of at-speed test sequences...
Irith Pomeranz, Sudhakar M. Reddy
ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
16 years 1 months ago
Fast wire length estimation by net bundling for block placement
The wire length estimation is the bottleneck of packing based block placers. To cope with this problem, we present a fast wire length estimation method in this paper. The key idea...
Tan Yan, Hiroshi Murata
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