Today’s Application Specific Instruction-set Processor (ASIP) design methodology often employs centralized Architecture Description Language (ADL) processor models, from which s...
Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Ra...
: This paper describes an architecture for differentiation of Quality of Service in heterogeneous wireless-wired networks. This architecture applies an “all-IP” paradigm, with ...
Janusz Gozdecki, Piotr Pacyna, Victor Marques, Rui...
We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...
Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhan...
Abstract. We solve the problem of extending Bird and Paterson’s generalized folds for nested datatypes and its dual to inductive and coinductive constructors of arbitrarily high ...
Flash Memory is a desirable candidate for main memory replacement in embedded systems due to its low leakage power consumption, higher density and non-volatility characteristics. ...
Liang Shi, Chun Jason Xue, Jingtong Hu, Wei-Che Ts...