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114
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SAMOS
2004
Springer
15 years 8 months ago
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting
Today’s Application Specific Instruction-set Processor (ASIP) design methodology often employs centralized Architecture Description Language (ADL) processor models, from which s...
Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Ra...
209
Voted
ARTQOS
2003
Springer
15 years 8 months ago
An IP QoS Architecture for 4G Networks
: This paper describes an architecture for differentiation of Quality of Service in heterogeneous wireless-wired networks. This architecture applies an “all-IP” paradigm, with ...
Janusz Gozdecki, Piotr Pacyna, Victor Marques, Rui...
121
Voted
ICS
2005
Tsinghua U.
15 years 8 months ago
A NUCA substrate for flexible CMP cache sharing
We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...
Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhan...
112
Voted
FOSSACS
2003
Springer
15 years 8 months ago
Generalized Iteration and Coiteration for Higher-Order Nested Datatypes
Abstract. We solve the problem of extending Bird and Paterson’s generalized folds for nested datatypes and its dual to inductive and coinductive constructors of arbitrarily high ...
Andreas Abel, Ralph Matthes, Tarmo Uustalu
GLVLSI
2010
IEEE
187views VLSI» more  GLVLSI 2010»
15 years 7 months ago
Write activity reduction on flash main memory via smart victim cache
Flash Memory is a desirable candidate for main memory replacement in embedded systems due to its low leakage power consumption, higher density and non-volatility characteristics. ...
Liang Shi, Chun Jason Xue, Jingtong Hu, Wei-Che Ts...