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» Approach for physical design in sub-100 nm era
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34
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ISCAS
2005
IEEE
133views Hardware» more  ISCAS 2005»
15 years 3 months ago
Approach for physical design in sub-100 nm era
Hiroo Masuda, Shin-ichi Ohkawa, Masakazu Aoki
ISQED
2003
IEEE
96views Hardware» more  ISQED 2003»
15 years 3 months ago
New DFM Approach Abstracts AltPSM Lithography Requirements for sub-100nm IC Design Domains
Approach Abstracts AltPSM Lithography Requirements for sub-100nm IC Design Domains Pradiptya Ghosh, Chung-shin Kang, Michael Sanie and David Pinto Numerical Technologies, 70 West P...
Pradiptya Ghosh, Chung-shin Kang, Michael Sanie, D...
GECCO
2007
Springer
169views Optimization» more  GECCO 2007»
15 years 3 months ago
An evolutionary platform for developing next-generation electronic circuits
In this paper, a new method for evolving simple electronic circuits is discussed, with the aim of improving the reliability and performance of basic circuit blocks. Next-generatio...
James A. Hilder, Andy M. Tyrrell
57
Voted
DAC
2004
ACM
15 years 10 months ago
Compact thermal modeling for temperature-aware design
Thermal design in sub-100nm technologies is one of the major challenges to the CAD community. In this paper, we first introduce the idea of temperature-aware design. We then propo...
Wei Huang, Mircea R. Stan, Kevin Skadron, Karthik ...
71
Voted
DAC
2004
ACM
15 years 10 months ago
Statistical optimization of leakage power considering process variations using dual-Vth and sizing
timing analysis tools to replace standard deterministic static timing analyzers whereas [8,27] develop approaches for the statistical estimation of leakage power considering within...
Ashish Srivastava, Dennis Sylvester, David Blaauw