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ICCD
2004
IEEE
119views Hardware» more  ICCD 2004»
15 years 8 months ago
Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems
Three dimensional vertically integrated systems allow active devices to be placed on multiple device layers. In recent years, a number of research efforts have addressed physical ...
Madhubanti Mukherjee, Ranga Vemuri
DATE
2009
IEEE
131views Hardware» more  DATE 2009»
15 years 6 months ago
Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling
this paper proposes a novel Process Variation Aware SRAM architecture designed to inherently support voltage scaling. The peripheral circuitry of the SRAM is modified to selectivel...
Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, F...
IPPS
2008
IEEE
15 years 6 months ago
Reducing the run-time of MCMC programs by multithreading on SMP architectures
The increasing availability of multi-core and multiprocessor architectures provides new opportunities for improving the performance of many computer simulations. Markov Chain Mont...
Jonathan M. R. Byrd, Stephen A. Jarvis, A. H. Bhal...
IPPS
2005
IEEE
15 years 5 months ago
A Robust Interference Model for Wireless Ad-Hoc Networks
Among the foremost goals of topology control in wireless ad-hoc networks is interference reduction. This paper presents a receiver-centric interference model featuring two main ad...
Pascal von Rickenbach, Stefan Schmid, Roger Watten...
ICCD
2000
IEEE
87views Hardware» more  ICCD 2000»
15 years 4 months ago
Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks
This paper describes the application of binary and multivalued SPFD-based wire removal techniques for circuit implementations utilizing networks of PLAs. It has been shown that a ...
Subarnarekha Sinha, Sunil P. Khatri, Robert K. Bra...