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FCCM
2006
IEEE
125views VLSI» more  FCCM 2006»
15 years 6 months ago
A Multithreaded Soft Processor for SoPC Area Reduction
The growth in size and performance of Field Programmable Gate Arrays (FPGAs) has compelled System-on-aProgrammable-Chip (SoPC) designers to use soft processors for controlling sys...
Blair Fort, Davor Capalija, Zvonko G. Vranesic, St...
MSS
2005
IEEE
62views Hardware» more  MSS 2005»
15 years 5 months ago
Predictive Reduction of Power and Latency (PuRPLe)
Increasing efforts have been aimed towards the management of power as a critical system resource, and the disk can consume approximately a third of the power required for a typica...
Matthew Craven, Ahmed Amer
CIT
2006
Springer
15 years 3 months ago
A new collision resistant hash function based on optimum dimensionality reduction using Walsh-Hadamard transform
Hash functions play the most important role in various cryptologic applications, ranging from data integrity checking to digital signatures. Our goal is to introduce a new hash fu...
Barzan Mozafari, Mohammad Hasan Savoji
CF
2005
ACM
15 years 1 months ago
An efficient wakeup design for energy reduction in high-performance superscalar processors
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
Kuo-Su Hsiao, Chung-Ho Chen
BMCBI
2010
119views more  BMCBI 2010»
14 years 12 months ago
A comparison of internal validation techniques for multifactor dimensionality reduction
Background: It is hypothesized that common, complex diseases may be due to complex interactions between genetic and environmental factors, which are difficult to detect in high-di...
Stacey J. Winham, Andrew J. Slater, Alison A. Mots...