111 search results - page 6 / 23 » Approximating Low Latency Queueing Buffer Latency |
112
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ICDCS
1997
IEEE
15 years 6 months ago
1997
IEEE
Conventional implementations of CORBA communication middleware incur significant overhead when used for performance-sensitive applications over high-speed networks. As gigabit ne...
100
Voted
ISCA
2002
IEEE
15 years 6 months ago
2002
IEEE
Instruction window size is an important design parameter for many modern processors. Large instruction windows offer the potential advantage of exposing large amounts of instructi...
ICCD
2007
IEEE
15 years 10 months ago
2007
IEEE
This paper presents the Finished Store Buffer (or FSB), an alternative and position-insensitive approach for building a scalable store buffer for an out-of-order processor. Exploi...
117
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SIGMETRICS
2005
ACM
15 years 7 months ago
2005
ACM
Scalability considerations drive the switch fabric design to evolve from output queueing to input queueing and further to combined input and crosspoint queueing (CICQ). However, f...
97
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LCN
2005
IEEE
15 years 7 months ago
2005
IEEE
A combined input and crosspoint queued (CICQ) switch with a flow control latency of round-trip time (RTT) packets requires each crosspoint (CP) buffer to hold the RTT packets in o...