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124
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ICCAD
2004
IEEE
125views Hardware» more  ICCAD 2004»
16 years 1 months ago
Temporal floorplanning using the T-tree formulation
Improving logic capacity by time-sharing, dynamically reconfigurable FPGAs are employed to handle designs of high complexity and functionality. In this paper, we model each task ...
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
ICCAD
2001
IEEE
111views Hardware» more  ICCAD 2001»
16 years 1 months ago
Congestion Aware Layout Driven Logic Synthesis
In this paper, we present novel algorithms that effectively combine physical layout and early logic synthesis to improve overall design quality. In addition, we employ partitionin...
Thomas Kutzschebauch, Leon Stok
142
Voted
PADL
2010
Springer
16 years 1 months ago
An Ode to Arrows
Abstract. We study a number of embedded DSLs for autonomous ordinary differential equations (autonomous ODEs) in Haskell. A naive implementation based on the lazy tower of derivat...
Hai Liu, Paul Hudak
CVPR
2010
IEEE
16 years 16 days ago
Fast Globally Optimal 2D Human Detection with Loopy Graph Models
This paper presents an algorithm for recovering the globally optimal 2D human figure detection using a loopy graph model. This is computationally challenging because the time comp...
Tai-Peng Tian, Stan Sclaroff
CVPR
2010
IEEE
16 years 3 hour ago
A Novel Riemannian Framework for Shape Analysis of 3D Objects
In this paper we introduce a novel Riemannian framework for shape analysis of parameterized surfaces. We derive a distance function between any two surfaces that is invariant to r...
Sebastian Kurtek, Eric Klassen, Anuj Srivastava, Z...
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