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MICRO
2003
IEEE
106views Hardware» more  MICRO 2003»
15 years 5 months ago
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
This paper proposes and evaluates single-ISA heterogeneous multi-core architectures as a mechanism to reduce processor power dissipation. Our design incorporates heterogeneous cor...
Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, P...
DAC
1999
ACM
15 years 4 months ago
Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications
Dual threshold technique has been proposed to reduce leakage power in low voltage and low power circuits by applying a high threshold voltage to some transistors in non-critical p...
Liqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye,...
DFT
2005
IEEE
132views VLSI» more  DFT 2005»
15 years 1 months ago
Low Power BIST Based on Scan Partitioning
A built-in self-test (BIST) scheme is presented which both reduces overhead for detecting random-pattern-resistant (r.p.r.) faults as well as reduces power consumption during test...
Jinkyu Lee, Nur A. Touba
CSREAESA
2003
15 years 1 months ago
A Comparative Study of Dynamic Voltage Scaling Techniques for Low-Power Video Decoding
This paper presents a comparison of power-aware video decoding techniques that utilize Dynamic Voltage Scaling (DVS) capability. Three techniques were simulated and compared in te...
Eriko Nurvitadhi, Ben Lee, Chansu Yu, Myungchul Ki...
PR
2007
101views more  PR 2007»
14 years 11 months ago
Use of power law models in detecting region of interest
In this paper, we shall address the issue of semantic extraction of different regions of interest. The proposed approach is based on statistical methods and models inspired from l...
Yves Caron, Pascal Makris, Nicole Vincent