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153
Voted
PPOPP
2009
ACM
16 years 4 months ago
2009
ACM
The efficient mapping of program parallelism to multi-core processors is highly dependent on the underlying architecture. This paper proposes a portable and automatic compiler-bas...
143
Voted
SPAA
2009
ACM
16 years 4 months ago
2009
ACM
We consider buffer management of unit packets with deadlines for a multi-port device with reconfiguration overhead. The goal is to maximize the throughput of the device, i.e., the...
121
Voted
PODC
2009
ACM
16 years 4 months ago
2009
ACM
Transactional memories are typically speculative and rely on contention managers to cure conflicts. This paper explores a complementary approach that prevents conflicts by schedul...
114
Voted
HPCA
2009
IEEE
16 years 4 months ago
2009
IEEE
Several recent processor designs have proposed to enhance performance by increasing the clock frequency to the point where timing faults occur, and by adding error-correcting supp...
132
Voted
HPCA
2009
IEEE
16 years 4 months ago
2009
IEEE
Heterogeneous multicores, such as Cell BE processors and GPGPUs, typically do not have caches for their accelerator cores because coherence traffic, cache misses, and latencies fr...