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IPPS
2010
IEEE
14 years 8 months ago
A PRAM-NUMA model of computation for addressing low-TLP workloads
It is possible to implement the parallel random access machine (PRAM) on a chip multiprocessor (CMP) efficiently with an emulated shared memory (ESM) architecture to gain easy par...
Martti Forsell
WMPI
2004
ACM
15 years 3 months ago
SCIMA-SMP: on-chip memory processor architecture for SMP
Abstract. In this paper, we propose a processor architecture with programmable on-chip memory for a high-performance SMP (symmetric multi-processor) node named SCIMA-SMP (Software ...
Chikafumi Takahashi, Masaaki Kondo, Taisuke Boku, ...
ISSS
1999
IEEE
168views Hardware» more  ISSS 1999»
15 years 2 months ago
Automatic Architectural Synthesis of VLIW and EPIC Processors
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
AOSD
2009
ACM
15 years 1 months ago
A generic and reflective debugging architecture to support runtime visibility and traceability of aspects
In this paper we present a generic, mirror-based debugging architecture that supports runtime visibility and traceability of aspect oriented (AO) software systems. Runtime visibil...
Wouter De Borger, Bert Lagaisse, Wouter Joosen
SAC
2010
ACM
15 years 5 months ago
A real-time architecture design language for multi-rate embedded control systems
This paper presents a language dedicated to the description of the software architecture of complex embedded control systems. The language relies on the synchronous approach but e...
Julien Forget, Frédéric Boniol, Davi...