1308 search results - page 197 / 262 » Architectural Support for Dynamic Linking |
129
click to vote
SOSP
2003
ACM
16 years 1 months ago
2003
ACM
This paper presents Capriccio, a scalable thread package for use with high-concurrency servers. While recent work has advocated event-based systems, we believe that threadbased sy...
158
click to vote
SP
2010
IEEE
15 years 2 months ago
2010
IEEE
A program is defined to be noninterferent if its outputs cannot be influenced by inputs at a higher security level than their own. Various researchers have demonstrated how this pr...
136
click to vote
HPCA
2006
IEEE
16 years 4 months ago
2006
IEEE
In high-end processors, increasing the number of in-flight instructions can improve performance by overlapping useful processing with long-latency accesses to the main memory. Buf...
134
click to vote
HIPEAC
2009
Springer
15 years 11 months ago
2009
Springer
Developing streaming applications on heterogenous multi-processor architectures like the Cell is difficult. Currently, application developers need to know about hardware details t...
107
click to vote
DATE
2009
IEEE
15 years 11 months ago
2009
IEEE
this paper proposes a novel Process Variation Aware SRAM architecture designed to inherently support voltage scaling. The peripheral circuitry of the SRAM is modified to selectivel...