493 search results - page 35 / 99 » Architectural Support for Dynamic Memory Management |
110
click to vote
IEEEINTERACT
2003
IEEE
15 years 3 months ago
2003
IEEE
Recent studies on program execution behavior reveal that a large amount of execution time is spent in small frequently executed regions of code. Whereas adaptive cache management ...
77
Voted
HPCA
2009
IEEE
15 years 10 months ago
2009
IEEE
As the last-level on-chip caches in chip-multiprocessors increase in size, the physical locality of on-chip data becomes important for delivering high performance. The non-uniform...
50
Voted
GCC
2003
Springer
15 years 2 months ago
2003
Springer
Web service based data exchange has been the trend of EAI. We can create Proxies to expose existing systems as web services. There have been some tools that can help users to const...
HIPEAC
2009
Springer
15 years 4 months ago
2009
Springer
Developing streaming applications on heterogenous multi-processor architectures like the Cell is difficult. Currently, application developers need to know about hardware details t...
HPCA
2008
IEEE
15 years 10 months ago
2008
IEEE
The continued scaling of device dimensions and the operating voltage reduces the critical charge and thus natural noise tolerance level of transistors. As a result, circuits can p...