117 search results - page 10 / 24 » Architectural and technology influence on the optimal total ... |
DAC
2009
ACM
15 years 10 months ago
2009
ACM
Power consumption of system-level on-chip communications is becoming more significant in the overall system-on-chip (SoC) power as technology scales down. In this paper, we propos...
FPL
2001
Springer
15 years 2 months ago
2001
Springer
System and processor architectures depend on changes in technology. Looking ahead as die density and speed increase, power consumption and on chip interconnection delay become incr...
ANCS
2007
ACM
15 years 1 months ago
2007
ACM
Network-on-Chip (NoC) architectures provide a scalable solution to the wire delay constraints in deep submicron VLSI designs. Recent research into the optimization of NoC architec...
DAC
2000
ACM
15 years 10 months ago
2000
ACM
We have developed a function-level power estimation methodology for predicting the power dissipation of embedded software. For a given microprocessor core, we empirically build th...
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TVLSI
2010
14 years 4 months ago
2010
With the shrinking of technology feature sizes, the share of leakage in total power consumption of digital systems continues to grow. Traditional dynamic voltage scaling (DVS) fail...