117 search results - page 11 / 24 » Architectural and technology influence on the optimal total ... |
MICRO
2005
IEEE
15 years 3 months ago
2005
IEEE
Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can b...
105
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DSD
2006
IEEE
15 years 3 months ago
2006
IEEE
The Advanced Encryption Standard (AES) algorithm has become the default choice for various security services in numerous applications. In this paper we present an AES encryption h...
ICCD
1999
IEEE
15 years 2 months ago
1999
IEEE
This paper describes a core-customization process of a CISC processor core for a given application program. It aims at the power reduction in the CISC processor core by fully util...
MICRO
2008
IEEE
15 years 4 months ago
2008
IEEE
Any architectural optimization aims at satisfying the end user. However, modern architectures execute with little to no knowledge about the individual user. If architectures could...
TC
2008
14 years 9 months ago
2008
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...