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ICCAD
2003
IEEE
152views Hardware» more  ICCAD 2003»
15 years 6 months ago
Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming...
Nam Sung Kim, David Blaauw, Trevor N. Mudge
GLVLSI
2007
IEEE
172views VLSI» more  GLVLSI 2007»
15 years 4 months ago
The effect of temperature on cache size tuning for low energy embedded systems
Energy consumption is a major concern in embedded computing systems. Several studies have shown that cache memories account for about 40% or more of the total energy consumed in t...
Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki ...
HPCA
2003
IEEE
15 years 10 months ago
Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks
Originally developed to connect processors and memories in multicomputers, prior research and design of interconnection networks have focused largely on performance. As these netw...
Li Shang, Li-Shiuan Peh, Niraj K. Jha
ICCD
2000
IEEE
80views Hardware» more  ICCD 2000»
15 years 2 months ago
Power-Sensitive Multithreaded Architecture
The power consumption of microprocessors is becoming increasingly important in design decisions, not only in mobile processors, but also now in high-performance processors. Power-...
John S. Seng, Dean M. Tullsen, George Cai
61
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VLSID
2006
IEEE
170views VLSI» more  VLSID 2006»
15 years 10 months ago
16-Bit Segmented Type Current Steering DAC for Video Applications
In this paper, 16-bit, 50 MHz Current Steering DAC is designed. This DAC is implemented using TSMC 0.35 ?m technology. An optimum segmentation is done of 16-bits into binary and t...
Gaurav Raja, Basabi Bhaumik