312 search results - page 15 / 63 » Architectural approaches to reduce leakage energy in caches |
101
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HPCA
2005
IEEE
16 years 2 months ago
2005
IEEE
Simultaneous multithreading (SMT) and chip multiprocessing (CMP) both allow a chip to achieve greater throughput, but their relative energy-efficiency and thermal properties are s...
144
Voted
DAC
1999
ACM
16 years 2 months ago
1999
ACM
In embedded system design, the designer has to choose an onchip memory configuration that is suitable for a specific application. To aid in this design choice, we present a memory...
122
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ICCAD
2009
IEEE
14 years 11 months ago
2009
IEEE
The emerging Spin Torque Transfer memory (STT-RAM) is a promising candidate for future on-chip caches due to STT-RAM's high density, low leakage, long endurance and high acce...
121
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DAC
2009
ACM
16 years 2 months ago
2009
ACM
Energy consumption is of significant concern in battery operated embedded systems. In the processors of such systems, the instruction cache consumes a significant fraction of the ...
113
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IEEEPACT
2003
IEEE
15 years 7 months ago
2003
IEEE
We present a technique for reducing the power dissipation in the course of writebacks and committments in a datapath that uses a dedicated architectural register file (ARF) to hol...