312 search results - page 18 / 63 » Architectural approaches to reduce leakage energy in caches |
113
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DAC
2008
ACM
15 years 1 months ago
2008
ACM
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...
ISLPED
2005
ACM
15 years 5 months ago
2005
ACM
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...
109
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ISSS
2002
IEEE
15 years 4 months ago
2002
IEEE
Adding a small loop cache to a microprocessor has been shown to reduce average instruction fetch energy for various sets of embedded system applications. With the advent of core-b...
105
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ISLPED
2010
ACM
14 years 12 months ago
2010
ACM
We have developed a system architecture, measuring and modeling techniques, and algorithms for on-line power and energy optimization and thermal management. The starting point for...
CF
2004
ACM
15 years 5 months ago
2004
ACM
Next generation architectures will require innovative solutions to reduce energy consumption. One of the trends we expect is more extensive utilization of compiler information dir...