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» Architectural approaches to reduce leakage energy in caches
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IWSOC
2003
IEEE
104views Hardware» more  IWSOC 2003»
15 years 5 months ago
Incorporating Pattern Prediction Technique for Energy Efficient Filter Cache Design
: - A filter cache is proposed at a higher level than the L1 (main) cache in the memory hierarchy and is much smaller. The typical size of filter cache is of the order of 512 Bytes...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...
ISLPED
2004
ACM
137views Hardware» more  ISLPED 2004»
15 years 5 months ago
Location cache: a low-power L2 cache system
While set-associative caches incur fewer misses than directmapped caches, they typically have slower hit times and higher power consumption, when multiple tag and data banks are p...
Rui Min, Wen-Ben Jone, Yiming Hu
HPCA
2011
IEEE
14 years 3 months ago
Archipelago: A polymorphic cache design for enabling robust near-threshold operation
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
EDBT
2009
ACM
158views Database» more  EDBT 2009»
15 years 3 months ago
An approach to detecting relevant updates to cached data using XML and active databases
Client/server information systems use caching techniques to reduce the volume of transmitted data as well as response time and, especially in the case of systems with mobile clien...
Essam Mansour, Hagen Höpfner
DAC
2005
ACM
16 years 22 days ago
Enhanced leakage reduction Technique by gate replacement
Input vector control (IVC) technique utilizes the stack effect in CMOS circuit to apply the minimum leakage vector (MLV) to the circuit at the sleep mode to reduce leakage. Additi...
Lin Yuan, Gang Qu