Sciweavers

312 search results - page 24 / 63
» Architectural approaches to reduce leakage energy in caches
Sort
View
TCSV
2002
89views more  TCSV 2002»
15 years 1 months ago
Reducing energy dissipation of frame memory by adaptive bit-width compression
Abstract--In this paper, we propose a new architectural technique to reduce energy dissipation of frame memory through adaptive bitwith compression. Unlike related approaches, the ...
Vasily G. Moshnyaga
102
Voted
EUC
2006
Springer
15 years 5 months ago
Saving Register-File Leakage Power by Monitoring Instruction Sequence in ROB
- Modern portable or embedded systems support more and more complex applications. These applications make embedded devices require not only low powerconsumption, but also high comp...
Wann-Yun Shieh, Hsin-Dar Chen
151
Voted
ISLPED
2010
ACM
128views Hardware» more  ISLPED 2010»
14 years 11 months ago
Rank-aware cache replacement and write buffering to improve DRAM energy efficiency
DRAM power and energy efficiency considerations are becoming increasingly important for low-power and mobile systems. Using lower power modes provided by commodity DRAM chips redu...
Ahmed M. Amin, Zeshan Chishti
ICCD
2005
IEEE
110views Hardware» more  ICCD 2005»
15 years 10 months ago
Near-memory Caching for Improved Energy Consumption
Main memory has become one of the largest contributors to overall energy consumption and offers many opportunities for power/energy reduction. In this paper, we propose a PowerAw...
Nevine AbouGhazaleh, Bruce R. Childers, Daniel Mos...
ICS
2005
Tsinghua U.
15 years 7 months ago
Disk layout optimization for reducing energy consumption
Excessive power consumption is becoming a major barrier to extracting the maximum performance from high-performance parallel systems. Therefore, techniques oriented towards reduci...
Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir