312 search results - page 28 / 63 » Architectural approaches to reduce leakage energy in caches |
106
click to vote
PCI
2005
Springer
15 years 5 months ago
2005
Springer
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...
80
Voted
DAC
2000
ACM
16 years 22 days ago
2000
ACM
In this paper, we presen t the design and use of a comprehensiv e framework, SimplePower, for evaluating the e ect of high-level algorithmic, architectural, and compilation tradeo...
100
click to vote
IJES
2007
14 years 11 months ago
2007
Abstract: Main memory has become one of the largest contributors to overall energy consumption and offers many opportunities for power/energy reduction. In this paper, we propose ...
ICCD
2007
IEEE
15 years 8 months ago
2007
IEEE
Low energy and small switch area usage are two of the important design objectives in FPGA global routing architecture design. This paper presents an improved MCF model based CAD ...
106
click to vote
GLVLSI
2008
IEEE
15 years 6 months ago
2008
IEEE
Due to the large contribution of the memory subsystem to total system power, the memory subsystem is highly amenable to customization for reduced power/energy and/or improved perf...