312 search results - page 29 / 63 » Architectural approaches to reduce leakage energy in caches |
103
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PACS
2000
Springer
15 years 3 months ago
2000
Springer
Power dissipation is a major concern not only for portable systems, but also for high-performance systems. In the past, energy consumption and processor heating was reduced mainly...
ICCD
2007
IEEE
15 years 8 months ago
2007
IEEE
This paper proposes a new low power cache architecture that utilizes fault tolerance to allow aggressively reduced voltage levels. The fault tolerant overhead circuits consume lit...
ICS
2005
Tsinghua U.
15 years 5 months ago
2005
Tsinghua U.
We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...
MICRO
2010
IEEE
14 years 9 months ago
2010
IEEE
Energy efficiency is a primary concern for microprocessor designers. A very effective approach to improving the energy efficiency of a chip is to lower its supply voltage to very ...
115
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TCAD
2002
14 years 11 months ago
2002
In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power ...