312 search results - page 30 / 63 » Architectural approaches to reduce leakage energy in caches |
ICCAD
2002
IEEE
15 years 8 months ago
2002
IEEE
Dynamic voltage scaling (DVS) reduces the power consumption of processors when peak performance is unnecessary. However, the achievable power savings by DVS alone is becoming limi...
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VLSID
2008
IEEE
16 years 5 days ago
2008
IEEE
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
DAC
2004
ACM
16 years 23 days ago
2004
ACM
timing analysis tools to replace standard deterministic static timing analyzers whereas [8,27] develop approaches for the statistical estimation of leakage power considering within...
APCSAC
2003
IEEE
15 years 5 months ago
2003
IEEE
This paper proposes an approach for reducing access count to register-files based on operand data reuse. The key idea is to compare source and destination operands of the current ...
DATE
2007
IEEE
15 years 6 months ago
2007
IEEE
This paper presents a task scheduling method for reliable cache architectures (RCAs) of multiprocessor systems. The RCAs dynamically switch their operation modes for reducing the ...