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» Architectural approaches to reduce leakage energy in caches
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DATE
2002
IEEE
104views Hardware» more  DATE 2002»
15 years 4 months ago
Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors
In this paper, we suggest hardware-assisted data compression as a tool for reducing energy consumption of core-based embedded systems. We propose a novel and e cient architecture ...
Luca Benini, Davide Bruni, Alberto Macii, Enrico M...
CC
2007
Springer
126views System Software» more  CC 2007»
15 years 6 months ago
An Array Allocation Scheme for Energy Reduction in Partitioned Memory Architectures
This paper presents a compiler technique that reduces the energy consumption of the memory subsystem, for an off-chip partitioned memory architecture having multiple memory banks ...
K. Shyam, R. Govindarajan
CASES
2009
ACM
15 years 6 months ago
An accelerator-based wireless sensor network processor in 130nm CMOS
Networks of ultra-low-power nodes capable of sensing, computation, and wireless communication have applications in medicine, science, industrial automation, and security. Over the...
Mark Hempstead, Gu-Yeon Wei, David Brooks
IJNSEC
2008
127views more  IJNSEC 2008»
14 years 11 months ago
Reducing Communication Overhead for Wireless Roaming Authentication: Methods and Performance Evaluation
The protocol design for wireless roaming authentication is challenging because of the key management regarding users and home/visited networks. In this paper, we present two authe...
Men Long, Chwan-Hwa John Wu, J. David Irwin
DAC
2004
ACM
16 years 23 days ago
Leakage-and crosstalk-aware bus encoding for total power reduction
Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC de...
Harmander Deogun, Rajeev R. Rao, Dennis Sylvester,...