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IEEEPACT
2006
IEEE
15 years 5 months ago
Self-checking instructions: reducing instruction redundancy for concurrent error detection
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal
ISCA
2010
IEEE
305views Hardware» more  ISCA 2010»
15 years 4 months ago
Rethinking DRAM design and organization for energy-constrained multi-cores
DRAM vendors have traditionally optimized the cost-perbit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, wher...
Aniruddha N. Udipi, Naveen Muralimanohar, Niladris...
PACS
2004
Springer
141views Hardware» more  PACS 2004»
15 years 5 months ago
Energy-Aware Data Prefetching for General-Purpose Programs
There has been intensive research on data prefetching focusing on performance improvement, however, the energy aspect of prefetching is relatively unknown. Our experiments show th...
Yao Guo, Saurabh Chheda, Israel Koren, C. Mani Kri...
DATE
2004
IEEE
146views Hardware» more  DATE 2004»
15 years 3 months ago
Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies
In multimedia and other streaming applications a significant portion of energy is spent on data transfers. Exploiting data reuse opportunities in the application, we can reduce th...
Ilya Issenin, Erik Brockmeyer, Miguel Miranda, Nik...
GLOBECOM
2006
IEEE
15 years 5 months ago
Honeycomb Architecture for Energy Conservation in Wireless Sensor Networks
— Reducing energy consumption has been a recent focus of wireless sensor network research. Topology control explores the potential that a dense network has for energy savings. On...
Ren Ping Liu, Glynn Rogers, Sihui Zhou