312 search results - page 36 / 63 » Architectural approaches to reduce leakage energy in caches |
CC
2003
Springer
15 years 5 months ago
2003
Springer
Cache memories were invented to decouple fast processors from slow memories. However, this decoupling is only partial, and many researchers have attempted to improve cache use by p...
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HPCA
2006
IEEE
16 years 4 days ago
2006
IEEE
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
HPCA
2005
IEEE
15 years 5 months ago
2005
IEEE
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
MICRO
2009
IEEE
15 years 6 months ago
2009
IEEE
3D-integration is a promising technology to help combat the “Memory Wall” in future multi-core processors. Past work has considered using 3D-stacked DRAM as a large last-level...
DAC
2006
ACM
16 years 22 days ago
2006
ACM
Three-dimensional integrated circuits (3DICs) have the potential to reduce interconnect lengths and improve digital system performance. However, heat removal is more difficult in ...