312 search results - page 38 / 63 » Architectural approaches to reduce leakage energy in caches |
HPCA
2008
IEEE
16 years 4 days ago
2008
IEEE
Power-Efficient DRAM Speculation (PEDS) is a power optimization targeted at broadcast-based sharedmemory multiprocessor systems that speculatively access DRAM in parallel with the...
104
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DATE
2008
IEEE
15 years 6 months ago
2008
IEEE
Functional, instruction-based self-testing of microprocessors has recently emerged as an effective alternative or supplement to other testing approaches, and is progressively adop...
109
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HPCA
2008
IEEE
16 years 4 days ago
2008
IEEE
This paper describes a comprehensive approach for using the memory controller to improve DRAM energy efficiency and manage DRAM power. We make three contributions: (1) we describe...
DATE
2002
IEEE
15 years 4 months ago
2002
IEEE
Intra-iteration data reuse occurs when multiple array references exhibit data reuse in a single loop iteration. An optimizing compiler can exploit this reuse by clustering (in the...
101
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CODES
2008
IEEE
15 years 6 months ago
2008
IEEE
In this paper we present a framework for a distributed and very low-cost implementation of synchronization controllers and protocols for embedded multiprocessors. The proposed arc...