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» Architectural approaches to reduce leakage energy in caches
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ASAP
2003
IEEE
107views Hardware» more  ASAP 2003»
15 years 5 months ago
Energy Aware Register File Implementation through Instruction Predecode
The register file is a power-hungry device in modern architectures. Current research on compiler technology and computer architectures encourages the implementation of larger dev...
José L. Ayala, Marisa Luisa López-Va...
APCSAC
2004
IEEE
15 years 3 months ago
Initial Experiences with Dreamy Memory and the RAMpage Memory Hierarchy
The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory. This paper is a first look at the value of RAMpage to ...
Philip Machanick
CASES
2003
ACM
15 years 5 months ago
A low-power accelerator for the SPHINX 3 speech recognition system
Accurate real-time speech recognition is not currently possible in the mobile embedded space where the need for natural voice interfaces is clearly important. The continuous natur...
Binu K. Mathew, Al Davis, Zhen Fang
99
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HICSS
2005
IEEE
178views Biometrics» more  HICSS 2005»
15 years 5 months ago
The Entity Container - An Object-Oriented and Model-Driven Persistency Cache
Data persistency is a fundamental, but complex aspect of a modern software development process. Therefore, in order to reduce development costs and improve a system’s quality, s...
Gernot Schmoelzer, Stefan Mitterdorfer, Christian ...
TC
2010
14 years 6 months ago
A Counter Architecture for Online DVFS Profitability Estimation
Dynamic voltage and frequency scaling (DVFS) is a well known and effective technique for reducing power consumption in modern microprocessors. An important concern though is to est...
Stijn Eyerman, Lieven Eeckhout