312 search results - page 41 / 63 » Architectural approaches to reduce leakage energy in caches |
144
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HPCA
2006
IEEE
16 years 4 days ago
2006
IEEE
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
103
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CASES
2006
ACM
15 years 5 months ago
2006
ACM
In this paper, we propose a fully automatic dynamic scratchpad memory (SPM) management technique for instructions. Our technique loads required code segments into the SPM on deman...
108
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ASPLOS
1992
ACM
15 years 3 months ago
1992
ACM
Next generation computer systems will have gigabytes of physical memory and processors in the 200 MIPS range or higher. While this trend suggests that memory management for most p...
136
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DAC
2010
ACM
15 years 3 months ago
2010
ACM
We present a methodology for off-chip memory bandwidth minimization through application-driven L2 cache partitioning in multicore systems. A major challenge with multi-core system...
112
Voted
HPCA
2008
IEEE
16 years 4 days ago
2008
IEEE
Cache partitioning and sharing is critical to the effective utilization of multicore processors. However, almost all existing studies have been evaluated by simulation that often ...