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» Architectural approaches to reduce leakage energy in caches
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CASES
2006
ACM
15 years 5 months ago
Adapting compilation techniques to enhance the packing of instructions into registers
The architectural design of embedded systems is becoming increasingly idiosyncratic to meet varying constraints regarding energy consumption, code size, and execution time. Tradit...
Stephen Hines, David B. Whalley, Gary S. Tyson
SOSP
2001
ACM
15 years 8 months ago
Building Efficient Wireless Sensor Networks with Low-Level Naming
In most distributed systems, naming of nodes for low-level communication leveragestopologicallocation(such as node addresses) and is independentof any application. In this paper, ...
John S. Heidemann, Fabio Silva, Chalermek Intanago...
89
Voted
IPPS
2009
IEEE
15 years 6 months ago
Handling OS jitter on multicore multithreaded systems
Various studies have shown that OS jitter can degrade parallel program performance considerably at large processor counts. Most sources of system jitter fall broadly into 5 catego...
Pradipta De, Vijay Mann, Umang Mittaly
86
Voted
ACMMSP
2004
ACM
92views Hardware» more  ACMMSP 2004»
15 years 5 months ago
Instruction combining for coalescing memory accesses using global code motion
Instruction combining is an optimization to replace a sequence of instructions with a more efficient instruction yielding the same result in a fewer machine cycles. When we use it...
Motohiro Kawahito, Hideaki Komatsu, Toshio Nakatan...
CODES
2010
IEEE
14 years 9 months ago
A greedy buffer allocation algorithm for power-aware communication in body sensor networks
Monitoring human movements using wireless sensory devices promises to revolutionize the delivery of healthcare services. In spite of their potentials for many application domains,...
Hassan Ghasemzadeh, Roozbeh Jafari