312 search results - page 59 / 63 » Architectural approaches to reduce leakage energy in caches |
103
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MM
2003
ACM
15 years 5 months ago
2003
ACM
Optimizing user experience for streaming video applications on handheld devices is a significant research challenge. In this paper, we propose an integrated power management appr...
96
Voted
DAC
2008
ACM
15 years 1 months ago
2008
ACM
The problem attacked in this paper is one of automatically mapping an application onto a Network-on-Chip (NoC) based chip multiprocessor (CMP) architecture in a locality-aware fas...
116
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RTAS
2010
IEEE
14 years 10 months ago
2010
IEEE
—Hardware-managed caches introduce large amounts of timing variability, complicating real-time system design. One alternative is a memory system with scratchpad memories which im...
CODES
1999
IEEE
15 years 4 months ago
1999
IEEE
Reducing power consumption is critical in many system designs. Dynamic power management is an effective approach to decrease power without significantly degrading performance. Pow...
113
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ISCA
2009
IEEE
15 years 6 months ago
2009
IEEE
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...