312 search results - page 5 / 63 » Architectural approaches to reduce leakage energy in caches |
DSD
2003
IEEE
15 years 5 months ago
2003
IEEE
With shrinking feature size of silicon fabrication technology, architects are putting more and more logic into a single die. While one might opt to use these transistors for build...
CASES
2006
ACM
15 years 5 months ago
2006
ACM
Virtual caches are employed as L1 caches of both high performance and embedded processors to meet their short latency requirements. However, they also introduce the synonym proble...
118
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ICCD
2007
IEEE
15 years 3 months ago
2007
IEEE
The emerging trend of larger number of cores or processors on a single chip in the server, desktop, and mobile notebook platforms necessarily demands larger amount of on-chip last...
109
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DAC
2002
ACM
16 years 20 days ago
2002
ACM
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
ISLPED
2009
ACM
15 years 6 months ago
2009
ACM
The design trend of caches in modern processors continues to increase their capacity with higher associativity to cope with large data footprint and take advantage of feature size...