In this paper we present a state dependent analytical leakage power model for FPGAs. The model accounts for subthreshold leakage and gate leakage in FPGAs, since these are the two...
— We extend a 3D differential-operator-based filter architecture to a 3D IIR FPGA filter circuit implementation employing a recently proposed scanned-array method, which uses a s...
In this work, we parameterize and explore the interconnect structure of pipelined FPGAs. Specifically, we explore the effects of interconnect register population, length of regist...
Akshay Sharma, Katherine Compton, Carl Ebeling, Sc...
This paper discusses fault-tolerant techniques for SRAM-based FPGAs. These techniques can be based on circuit level modifications, with obvious modifications in the programmable a...
Fernanda Lima Kastensmidt, Gustavo Neuberger, Luig...
This paper describes a technique that reduces dynamic power in FPGAs by reducing the number of glitches in the global routing resources. The technique involves adding programmable...
Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wil...