110 search results - page 1 / 22 » Architectural simulation for a programmable DSP chip set |
90
Voted
ASPDAC
1995
ACM
15 years 8 months ago
1995
ACM
125
Voted
DAC
1999
ACM
16 years 5 months ago
1999
ACM
Abstract { This paper presents the machine description language LISA for the generation of bitand cycle accurate models of DSP processors. Based on a behavioral operation descripti...
143
click to vote
VLSID
2004
IEEE
16 years 5 months ago
2004
IEEE
The design of any application on a configurable System-on-a-Chip (SoC) like Atmel's FPSLIC is subject to a lot of constraints stemming from requirements of the application an...
147
click to vote
NOCS
2009
IEEE
15 years 11 months ago
2009
IEEE
This paper presents a many-core heterogeneous computational platform that employs a GALS compatible circuit-switched on-chip network. The platform targets streaming DSP and embedd...
156
Voted
IWSOC
2005
IEEE
15 years 10 months ago
2005
IEEE
A fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and a number flexible accelerators, connected via a con...