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» Architectural simulation for a programmable DSP chip set
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ISCAS
1994
IEEE
138views Hardware» more  ISCAS 1994»
15 years 1 months ago
High-Throughput Data Compressor Designs Using Content Addressable Memory
This paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units...
Ren-Yang Yang, Chen-Yi Lee
DAC
1995
ACM
15 years 1 months ago
Multi-way Partitioning for Minimum Delay for Look-Up Table Based FPGAs
In this paper we present a set cover based approach (SCP) to multi-way partitioning for minimum delay for Look-Up Table based FPGAs. SCP minimizes the number of chip-crossings on ...
Prashant Sawkar, Donald E. Thomas
VLSID
2000
IEEE
90views VLSI» more  VLSID 2000»
15 years 2 months ago
Performance Analysis of Systems with Multi-Channel Communication Architectures
This paper presents a novel system performance analysis technique to support the design of custom communication architectures for System-on-Chip ICs. Our technique fills a gap in...
Kanishka Lahiri, Sujit Dey, Anand Raghunathan
ICES
2001
Springer
107views Hardware» more  ICES 2001»
15 years 2 months ago
Polymorphic Electronics
This paper introduces the concept of polymorphic electronics (polytronics) –referring to electronics with superimposed built-in functionality. A function change does not require ...
Adrian Stoica, Ricardo Salem Zebulum, Didier Keyme...
IPPS
2010
IEEE
14 years 7 months ago
Scalable multi-pipeline architecture for high performance multi-pattern string matching
Multi-pattern string matching remains a major performance bottleneck in network intrusion detection and anti-virus systems for high-speed deep packet inspection (DPI). Although Aho...
Weirong Jiang, Yi-Hua Edward Yang, Viktor K. Prasa...