110 search results - page 18 / 22 » Architectural simulation for a programmable DSP chip set |
ISCAS
2006
IEEE
15 years 3 months ago
2006
IEEE
– Increasing logic densities and clock frequencies on FPGAs lead to rapid increase in power density, which translates to higher on-chip temperature. In this paper, we investigate...
66
Voted
MICRO
2007
IEEE
15 years 3 months ago
2007
IEEE
Modern chip multiprocessors (CMPs) are designed to exploit both instruction-level parallelism (ILP) within processors and thread-level parallelism (TLP) within and across processo...
VLSI
2007
Springer
15 years 3 months ago
2007
Springer
In this paper, we present the way of fast and accurate estimation of software energy consumption in off-the-shelf processor using IPI(Inter-Prefetch Interval) energy model. In ou...
MICRO
2009
IEEE
15 years 4 months ago
2009
IEEE
Many-core scaling now faces a power wall. The gap between the number of cores that fit on a die and the number that can operate simultaneously under the power budget is rapidly i...
103
click to vote
CODES
2009
IEEE
15 years 1 months ago
2009
IEEE
Profilers play an important role in software/hardware design, optimization, and verification. Various approaches have been proposed to implement profilers. The most widespread app...