234 search results - page 33 / 47 » Architecture Implementation Using the Machine Description La... |
ACMMSP
2004
ACM
15 years 2 months ago
2004
ACM
Instruction combining is an optimization to replace a sequence of instructions with a more efficient instruction yielding the same result in a fewer machine cycles. When we use it...
ISCA
1998
IEEE
15 years 1 months ago
1998
IEEE
The design challenge for large-scale multiprocessors is (1) to minimize communication overhead, (2) allow communication to overlap computation, and (3) coordinate the two without ...
125
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OOPSLA
2010
Springer
14 years 8 months ago
2010
Springer
Heterogeneous multi-core processors, such as the IBM Cell processor, can deliver high performance. However, these processors are notoriously difficult to program: different cores...
103
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TPHOL
2009
IEEE
15 years 4 months ago
2009
IEEE
Abstract. We present a comprehensive set of tactics that make it practical to use separation logic in a proof assistant. These tactics enable the verification of partial correctne...
ASPLOS
1991
ACM
15 years 1 months ago
1991
ACM
Caches enhance the performance of multiprocessors by reducing network trac and average memory access latency. However, cache-based systems must address the problem of cache coher...