1381 search results - page 3 / 277 » Architecture and Design of a High Performance SRAM for SOC D... |
IPPS
2006
IEEE
14 years 7 days ago
2006
IEEE
Current electronic system design requires to be concerned with power consumption consideration. However, in a lot of design tools, the application power consumption budget is esti...
DAC
2012
ACM
11 years 8 months ago
2012
ACM
Spin-Transfer Torque RAM (STT-RAM) is an emerging non-volatile memory (NVM) technology that has the potential to replace the conventional on-chip SRAM caches for designing a more ...
DATE
2010
IEEE
13 years 11 months ago
2010
IEEE
—In a conventional SoC designs, on-chip memories occupy more than the 50% of the total die area. 3D technology enables the distribution of logic and memories on separate stacked ...
ANCS
2009
ACM
13 years 4 months ago
2009
ACM
The problem of maintaining efficiently a large number (say millions) of statistics counters that need to be updated at very high speeds (e.g. 40 Gb/s) has received considerable re...
DFT
2004
IEEE
13 years 10 months ago
2004
IEEE
This paper proposes a test architecture aimed at reducing test time of distributed small embedded SRAMs (eSRAMs). This architecture improves the one proposed in [4, 5]. The improv...