130 search results - page 23 / 26 » Architecture and Evaluation of an Asynchronous Array of Simp... |
HPCA
2006
IEEE
14 years 6 months ago
2006
IEEE
Previous proposals for power-aware thread-level parallelism on chip multiprocessors (CMPs) mostly focus on multiprogrammed workloads. Nonetheless, parallel computation of a single...
ICCD
2000
IEEE
14 years 3 months ago
2000
IEEE
In superscalar architectures, out-of-order issue mechanisms increase performance by dynamically rescheduling instructions that cannot be statically reordered by the compiler. Whil...
RTSS
1999
IEEE
13 years 10 months ago
1999
IEEE
Previous timing analysis methods have assumed that the worst-case instruction execution time necessarily corresponds to the worst-case behavior. We show that this assumption is wr...
ASPLOS
2009
ACM
14 years 6 months ago
2009
ACM
Even though graphics processors (GPUs) are becoming increasingly popular for general purpose computing, current (and likely near future) generations of GPUs do not provide hardwar...
ISPDC
2010
IEEE
13 years 4 months ago
2010
IEEE
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...