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» Architecture and Implementation of an Embedded Wormhole
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RTAS
1997
IEEE
15 years 4 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford
DATE
2009
IEEE
189views Hardware» more  DATE 2009»
15 years 6 months ago
CUFFS: An instruction count based architectural framework for security of MPSoCs
—Multiprocessor System on Chip (MPSoC) architecture is rapidly gaining momentum for modern embedded devices. The vulnerabilities in software on MPSoCs are often exploited to caus...
Krutartha Patel, Sri Parameswaran, Roshan G. Ragel
CF
2009
ACM
15 years 6 months ago
Mapping the LU decomposition on a many-core architecture: challenges and solutions
Recently, multi-core architectures with alternative memory subsystem designs have emerged. Instead of using hardwaremanaged cache hierarchies, they employ software-managed embedde...
Ioannis E. Venetis, Guang R. Gao
RTAS
1998
IEEE
15 years 4 months ago
End-Host Architecture for QoS-Adaptive Communication
Proliferation of communication-intensive real-time applications with elastic" timeliness constraints, such as streaming stored video, requires a new design for endhost commun...
Tarek F. Abdelzaher, Kang G. Shin
DATE
2008
IEEE
145views Hardware» more  DATE 2008»
15 years 6 months ago
Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures
We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the route...
Mohammad Abdullah Al Faruque, Jörg Henkel