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» Architecture and synthesis for multi-cycle communication
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DAC
2009
ACM
15 years 10 months ago
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications
Power consumption of system-level on-chip communications is becoming more significant in the overall system-on-chip (SoC) power as technology scales down. In this paper, we propos...
Renshen Wang, Nan-Chi Chou, Bill Salefski, Chung-K...
71
Voted
ASPDAC
2008
ACM
94views Hardware» more  ASPDAC 2008»
14 years 11 months ago
Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival
A major trend in a modern system-on-chip design is a growing system complexity, which results in a sharp increase of communication traffic on the on-chip communication bus architec...
Sujan Pandey, Rolf Drechsler
79
Voted
ISSS
1998
IEEE
130views Hardware» more  ISSS 1998»
15 years 1 months ago
Communication and Interface Synthesis on a Rapid Prototyping Hardware/Software Codesign System
In this paper, we propose the target board architecture of a rapid prototyping embedded system based on hardware software codesign. The target board contains a TMS320C30 DSP proce...
Yin-Tsung Hwang, Yuan-Hung Wang
ICCAD
2002
IEEE
106views Hardware» more  ICCAD 2002»
15 years 6 months ago
Throughput-driven IC communication fabric synthesis
As the scale of system integration continues to grow, the on-chip communication becomes the ultimate bottleneck of system performance and the primary determinant of system archite...
Tao Lin, Lawrence T. Pileggi
87
Voted
ARCS
2008
Springer
14 years 11 months ago
Synthesis of Multi-dimensional High-Speed FIFOs for Out-of-Order Communication
Due to increasing complexity of modern real-time image processing applications, classical hardware development at register transfer level becomes more and more the bottleneck of te...
Joachim Keinert, Christian Haubelt, Jürgen Te...