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DATE
2007
IEEE
85views Hardware» more  DATE 2007»
16 years 1 days ago
Low-power warp processor for power efficient high-performance embedded systems
Researchers previously proposed warp processors, a novel architecture capable of transparently optimizing an executing application by dynamically re-implementing critical kernels ...
Roman L. Lysecky
FPL
2004
Springer
95views Hardware» more  FPL 2004»
15 years 11 months ago
Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded Processor
Abstract. This paper proposes an architecture that combines a contextswitching virtual configware/software SAT solver with an embedded processor to promote a tighter coupling betwe...
C. J. Tavares, C. Bungardean, G. M. Matos, Jos&eac...
FPL
1995
Springer
106views Hardware» more  FPL 1995»
15 years 9 months ago
Some Notes on Power Management on FPGA-Based Systems
Although the energy required to perform a logic operation has continuously dropped at least by ten orders of magnitude since early vacuumtube electronics [1], the increasing clock ...
Eduardo I. Boemo, Guillermo González de Riv...
ISPD
2007
ACM
128views Hardware» more  ISPD 2007»
15 years 7 months ago
X-architecture placement based on effective wire models
In this paper, we derive the X-half-perimeter wirelength (XHPWL) model for X-architecture placement and explore the effects of three different wire models on X-architecture plac...
Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang
ISPD
2005
ACM
205views Hardware» more  ISPD 2005»
15 years 11 months ago
Coupling aware timing optimization and antenna avoidance in layer assignment
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
Di Wu, Jiang Hu, Rabi N. Mahapatra