Sciweavers

134 search results - page 3 / 27
» Architecture driven circuit partitioning
Sort
View
DAC
1995
ACM
13 years 9 months ago
Performance-Driven Partitioning Using a Replication Graph Approach
Lung-Tien Liu, Ming-Ter Kuo, Chung-Kuan Cheng, T. ...
ICCAD
2002
IEEE
100views Hardware» more  ICCAD 2002»
14 years 3 months ago
Multi-objective circuit partitioning for cutsize and path-based delay minimization
– In this paper we present multi-objective hMetis partitioning for simultaneous cutsize and circuit delay minimization. We change the partitioning process itself by introducing a...
Cristinel Ababei, Navaratnasothie Selvakkumaran, K...
DAC
1994
ACM
13 years 10 months ago
A Modular Partitioning Approach for Asynchronous Circuit Synthesis
Asynchronous circuits are crucial in designing low power and high performance digital systems. In this paper, we present an ecient modular partitioning approach for asynchronous c...
Ruchir Puri, Jun Gu
TCAD
2010
154views more  TCAD 2010»
13 years 29 days ago
Performance-Driven Dual-Rail Routing Architecture for Structured ASIC Design Style
In recent years, structured application-specific integrated circuit (ASIC) design style has lessened the importance of mask cost. Multiple structured ASIC chip designs share the sa...
Fu-Wei Chen, Yi-Yu Liu
DAC
1997
ACM
13 years 10 months ago
Multilevel Circuit Partitioning
Recent work [2] [5] [11] [12] [14] has illustrated the promise of multilevel approaches for partitioning large circuits. Multilevel partitioning recursively clusters the instance ...
Charles J. Alpert, Jen-Hsin Huang, Andrew B. Kahng